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c-mos sddi video depacking (gate array)
- top view - CXD8987AR (1/4)
il11 156
155
150
145
140
135
130
125
120
115
110
105 157
160
165
170
175
180
185
190
195
200
205
208 1
5
10
15
20
25
30
35
40
45
50
52 104
100
95
90
85
80
75
70
65
60
55
53 v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v) gnd gnd gnd gnd gnd gnd gnd gnd v dd (+3.3 v) gnd gnd v dd (+3.3 v) v dd (+3.3 v) gnd v dd (+3.3 v) gnd v dd (+3.3 v) gnd gnd gnd v dd (+3.3 v) gnd v dd (+3.3 v) gnd v dd (+3.3 v) gnd
CXD8987AR (2/4) 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42 din9
din8
gnd
din7
din6
din5
din4
din3
din2
v dd
din1
din0
inf
inv
gnd
inh
inpty
vint
ven
aint
aen
pcerd
swdet
lnec
aselh1
gnd
v dd
rst
sysi07
sysi06
sysi05
sysi04
sysi03
sysi02
sysi01
sysi00
state1
gnd
state0
strb
cs
hrst i
i
? i
i
i
i
i
i
? i
i
i
i
? i
i
i
i
i
i
i
i
i
o
? ? i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
? i
i
i
o (v dd = +3.3 v) pin
no. i/o signal 43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84 v dd
int
atwrst
syswrst
atwe
syswe
vexist
gnd
aexist
cpucf
d1sel
inclk
mdout7
mdout6
mdout5
mdout4
mdout3
gnd
v dd
mdout2
mdout1
mdout0
mdosync
mdoerr
mdopty
wra
wrb
wea13
wea12
gnd
wea11
wea10
web13
web12
web11
web10
v dd
xsm
xtst
sdi0
sdo0
wea23 ? o
o
o
o
o
o
? o
o
o
i
o
o
o
o
o
? ? o
o
o
o
o
o
o
o
o
o
? o
o
o
o
o
o
? i
i
i
o
o pin
no. i/o signal 85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126 gnd
wea22
wea21
wea20
web23
web22
web21
web20
bselh2
obank1
bank1
gnd
v dd
obank2
bank2
md17
md16
md15
md14
md13
md12
md11
gnd
md10
msync1
merr1
mpty1
oea13
oea12
v dd
oea11
oea10
rea13
rea12
gnd
rea11
rea10
rstr1a
oeb13
oeb12
oeb11
oeb10 ? o
o
o
o
o
o
o
o
o
i
? ? o
i
i
i
i
i
i
i
i
? i
i
i
i
o
o
? o
o
o
o
? o
o
o
o
o
o
o pin
no. i/o signal 127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168 reb13
reb12
reb11
gnd
v dd
reb10
rstr1b
md27
md26
md25
md24
md23
md22
md21
md20
gnd
msync2
merr2
mpty2
oea23
v dd
oea22
oea21
oea20
rea23
rea22
rea21
gnd
rea20
rstr2a
oeb23
oeb22
oeb21
oeb20
reb23
reb22
reb21
gnd
v dd
reb20
rstr2b
osdrw o
o
o
? ? o
o
i
i
i
i
i
i
i
i
? i
i
i
o
? o
o
o
o
o
o
? o
o
o
o
o
o
o
o
o
? ? o
o
i pin
no. i/o signal 169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208 outfrm
dec17
dec16
dec15
dec14
dec13
dec12
gnd
dec11
dec10
dec1sync
dec1pty
dec1err
aselh2
v dd
xack
bck
xtck
dec27
dec26
gnd
dec25
dec24
dec23
dec22
dec21
dec20
dec2sync
dec2pty
dec2err
bselh1
gnd
v dd
outclk
test0
test1
test2
refhd
refvd
refcfi o
o
o
o
o
o
o
? o
o
o
o
o
o
? i
i
i
o
o
? o
o
o
o
o
o
o
o
o
o
? ? i
i
i
i
i
i
i pin
no. i/o signal
CXD8987AR (3/4) input
aen
aint
bank1, bank2
bck
cs
din0 - din9
inclk
inf
inh
inpty
inv
lnec
md10 - md17
md20 - md27
merr1, merr2
mpty1, mpty2
msync1, msync2
osdrw
outclk
pcerd
refcfi
refhd
refvd
rst
sdi0
state0, state1
strb
swdet
test0 - test2
ven
vint
xack
xsm
xtck
xtst
; attribute data enable
; attribute data interrupt
; fifo memory bank select1, 2
; test
; cpu i/f (chip select)
; sddi data
; input clock
; input frame pulse
; input h pulse
; input parity
; input v pulse
; fifo memory select
; fifo memory input data1
; fifo memory input data2
; fifo memory input error1, 2
; fifo memory input parity1, 2
; fifo memory input sync1, 2
; external lock
; output clock
; sddi error
; reference cf information
; reference hd
; reference vd
; reset
; test
; cpu i/f (mode select)
; cpu i/f (strobe)
; sddi switching detect
; test
; video data enable
; video data interrupt
; test
; test
; test
; test
CXD8987AR (4/4) output
aexist
aselh1, aselh2
atwe
atwrst
bselh1, bselh2
cpucf
d1sel
dec0 - dec17
dec1err
dec1pty
dec1sync
dec0 - dec27
dec2err
dec2pty
dec2sync
hrst
int
mdoerr
mdopty
mdosync
mdout0 - mdout7
obank1, obank2
oea10 - oea13
oea20 - oea23
oeb10 - oeb13
oeb20 - oeb23
outfrm
rea10 - rea13
rea20 - rea23
reb10 - reb13
reb20 - reb23
rstr1a
rstr1b
rstr2a
rstr2b
sdo0
syswe
syswrst
vexist
wea10 - wea13
wea20 - wea23
web10 - web13
web20 - web23
wra
wrb
input/output
sysio0 - sysio7
; attribute exist
; fifo memory read select (a)
; fifo memory write enable (attribute)
; fifo memory write reset (attribute)
; fifo memory read select (b)
; input cf pulse
; decoder select
; video stream data1
; stream error1
; stream parity1
; stream sync1
; video stream data2
; stream error2
; stream parity2
; stream sync2
; fifo memory write reset (1h delay)
; cpu interrupt
; fifo memory output error
; fifo memory output parity
; fifo memory output sync
; fifo memory output data
; fifo memory bank select1, 2
; fifo memory output enable (1a)
; fifo memory output enable (2a)
; fifo memory output enable (1b)
; fifo memory output enable (2b)
; output frame pulse
; fifo memory read enable (1a)
; fifo memory read enable (2a)
; fifo memory read enable (1b)
; fifo memory read enable (2b)
; fifo memory read reset (1a)
; fifo memory read reset (1b)
; fifo memory read reset (2a)
; fifo memory read reset (2b)
; test
; fifo memory write enable (sys)
; fifo memory write reset (sys)
; video data exist
; fifo memory write enable (1a)
; fifo memory write enable (2a)
; fifo memory write enable (1b)
; fifo memory write enable (2b)
; fifo memory write reset (a)
; fifo memory write reset (b)
; cpu i/f (address & data)
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